Modern integrated circuits such as VLSI devices are typically made up of a large number of functional components formed on a single circuit substrate, or die. An increasingly important aspect of integrated circuit design concerns the placement of these functional components and the organization of interconnective paths that provide for the transmission of electrical signals between these functional components. Various algorithms have been developed to optimize the layout and interconnection of the functional components in an integrated circuit. The design of suitable interconnective pathways on an integrated circuit is typically termed routing. One goal of routing is to connect the functional components of the chip using the shortest possible conductive paths available.
A class of paths termed Steiner trees has been developed as one method that is used in the physical design of integrated circuits to efficiently route multi-terminal interconnective nets. A Steiner tree for n demand points is a tree (a connected graph with no closed paths) made up of lines that interconnect all n demand points of the tree. A Steiner tree, unlike for example a spanning tree, may also contain additional vertices that are not among the n demand points, in order to achieve a shorter pathway among these n demand points. A rectilinear Steiner tree (RST) of n demand points may be characterized as a tree composed only of orthogonal line segments (typically termed edges) that interconnect all n demand points (which are located at vertices). A rectilinear Steiner tree (RST) is confined to an underlying grid type graph which has traditionally been defined as the intersections of orthogonal lines (usually horizontally and vertically oriented) that are drawn through the n demand points. A graph may be considered a pair of sets G=(V, E), where V is a set of vertices or points, and E is a set of edges between the vertices. Finding a minimum rectilinear Steiner tree (MRST) can be characterized as finding a Steiner tree whose edges are constrained to rectilinear shapes that in combination connect all of the desired points in the shortest path available.
Preferably, the interconnective paths of the various functional devices in an integrated circuit do not cross through the functional devices themselves. These functional components therefore represent obstacles on a chip that must be considered in routing. It is therefore advantageous to consider the general problem of finding an MRST in the presence of such obstacles. A rectilinear obstacle (referred to as "obstacle" in the remainder of this application) can be considered a region in a plane bounded by a polygon whose sides are parallel to some coordinate system. For example, all of the sides of the obstacle may be vertically or horizontally oriented (see FIG. 1). The problem of finding an MRST is a specific case of the more general problem of finding an MRST in the presence of rectilinear obstacles (MRSTO) with the number of obstacles equal to zero (0). Although there is extensive literature on the MRST problem, there previously was no solution for the general MRSTO problem.